Nojan is one of the smartest people I know working on EDA and it’s refreshing to see someone with real experience talk about the space which suffers from a lot of noise rn. The chip design life cycle is very long and one small change up stream in RTL can have a huge impact later on. I think the best way to tackle this is speed to either shorten the wall time of simulation tools or heuristic methods to estimate quickly as you go. Notice how I haven’t said anything really about AI lol. In EDA the tool time dominates so much that actually AI agents can’t iterate that fast, to draw an analogy it’s like if compiling your code took 9+ hours every time… long feedback loops lessen the impact of AI. Therefore, I share the opinion with him that throwing the current ai agents at the space won’t produce meaningfully better chips and in fact AI written RTL is some of the most dangerous and worst code AI can generate as it looks correct but most of the issues are met downstream when you can’t meet PPA targets. Looking forward to him & chipsage cooking. 🍳